The read cycle time for most modern processors is significantly less than the access time of many non-volatile semiconductor memory devices, including erasable programmable read-only-memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash EPROM. Consequently, to avoid reading incorrect data after addressing such a memory device, a computer system's processor must be delayed for a number of wait states before being allowed to read the device output. Because the processor is essentially idle during each wait state, it is desirable to minimize the number of wait states required for any given memory access to avoid wasting the computational resources of the computer system.
FIG. 1 is a diagram of the architecture of a prior art page-mode flash memory device 12 that can be accessed with a reduced number of wait states. Flash memory 12 includes a flash memory array 5 containing a plurality of flash memory cells, a sense amplifier circuit 7, a multiplexer 9 and an output buffer 11. Flash memory device 12 receives at least two externally generated signals: an address signal defined by constituent address bits A.sub.0-X, and an output-enable signal OE#. As shown in FIG. 1, high order address bits A.sub.2-X are asserted to address the flash memory array 5, while low order address bits A.sub.0-1 are asserted to multiplexer 9. High order address bits A.sub.2-X define a range of addresses within the flash memory array 5 referred to as a "page address", and the data values stored at respective addresses encompassed by the page address are referred to collectively as a "page of memory", or "page" for short. Flash memory array 5 is designed to output an entire page of memory at once in response to each new page address. The page of memory output by flash memory array 5 is referred to herein as the "pending page", and each constituent data value of the pending page is referred to as a "word". Each word of the pending page is amplified by sense amplifier circuit 7 and asserted at a respective input of multiplexer 9. Low order address bits A.sub.0-1 act as multiplexer select signals to select one of the words input to multiplexer 9, and multiplexer 9, in response, outputs the selected one of the words to buffer 11. Buffer 11 drives the constituent bits of the selected word onto a data bus upon receiving an active output-enable signal OE# from an external controller.
The most time-consuming access to page-mode flash memory device 12 occurs when the page address is changed from the previous access cycle. In that case, the full access time of the flash memory array is incurred to output a new page of memory. However, if only the lower order, "word select", address bits A.sub.0-1 are changed from the previous cycle, then the requested data is present in the already pending page of memory and the full flash memory array access time need not be incurred. In effect, the page-mode flash memory device 12 allows the flash memory array access time to be amortized over a number of successive memory read cycles in which the page address remains unchanged. Because retrieval of a full page of memory is frequently required, e.g., to fill a row of cache memory, the page-mode architecture 12 can be used to substantially reduce the average access time for the flash memory device.
FIG. 2 is a timing diagram 35 of a sequence of read operations performed on the prior art page-mode flash memory device of FIG. 1. The signals shown include master clock signal CLK, page address A.sub.2-X, word select address A.sub.0-1, chip enable CE#, output enable OE#, and data output DQ.sub.0-15. As stated above, the page address A.sub.2-X and word select address A.sub.0-1 are each constituents of a single address A.sub.0-X asserted by a processor. It will be appreciated that the precise number of bits included in page address A.sub.2-X or word select address A.sub.0-1 may vary between implementations. Gridlines coinciding with each rising edge of the master clock signal CLK are shown to delineate the respective cycle periods of the master clock signal CLK.
During a first cycle period T.sub.a of the master clock signal CLK, a new address, designated Address 0 and including bits A.sub.0-X, is input to the page-mode flash memory device. Due to bus capacitance, a settling time indicated by arrow 22 is required before page address A.sub.2-X and word select address A.sub.0-1 become valid. Once the page address A.sub.2-X becomes valid, address decode logic external to the flash memory device asserts chip enable CE# to enable the page address A.sub.2-X into the flash memory device. As indicated by arrow 24 a propagation delay is incurred before the chip enable CE# transitions to an active low potential. Chip enable CE# continues to be asserted at the active low potential so long as page address A.sub.2-X remains unchanged.
As indicated by arrow 26, cycles T.sub.w1, T.sub.w2, T.sub.w3 and T.sub.w4 of the master clock signal CLK are completed before the addressed word, Data 0, becomes valid. Master clock cycles T.sub.w1, T.sub.w2, T.sub.w3 and T.sub.w4 represent wait states required to allow the flash memory array to be accessed and during these wait states the processor is essentially idle. The output enable signal OE# transitions to an active low potential some time before Data 0 becomes valid to allow Data 0 to be output to a data bus. The processor reads Data 0 during cycle T.sub.d0 of the master clock signal CLK and then asserts a new address, Address 1, at the rising edge of the subsequent clock cycle, T.sub.w.
Assuming that Address 1 includes the same page address as Address 0, the page address asserted to the flash memory device during clock cycle T.sub.a remains valid so that signals chip enable CE# and output enable OE# remain active. Also, by virtue of the page mode architecture described in reference to FIG. 1, the already pending page of memory contains the data value, Data 1, indicated by Address 1. Consequently, the time required for Data 1 to become valid is significantly less than the time required for Data 0 to become valid. More specifically, as indicated by arrow 28, Data 1 becomes valid during the cycle T.sub.d1 of the master clock signal which immediately follows the clock cycle T.sub.w in which Address 1 was asserted. The consequence of the reduced time for Data 1 to become valid is a reduced read cycle time for Data 1 (two master clock cycles) compared to the read cycle time for Data 0 (six master clock cycles). As indicated by arrows 30 and 32, respectively, additional data values from the pending page of memory, Data 2 and Data 3, are also addressed and output within two master clock cycles each. Consequently, with the page-mode architecture, the total number of clock cycles required for the processor to read four data values from the flash memory device can be reduced from a possible twenty-four clock cycles (4 words.times.6 clock cycles per word) to twelve clock cycles.
Despite the savings in access time made possible by the page mode architecture, wait states are still required to read data from the flash memory device, even after the page of memory is pending. For example, referring to FIG. 2, each of the T.sub.w cycles of the master clock signal CLK that follow T.sub.d0, T.sub.d1, T.sub.d2 and T.sub.d3, respectively, represent wait states during which the processor is essentially idle.